FlexCAN
MPC5606S Microcontroller Reference Manual, Rev. 7
702 Freescale Semiconductor
FlexCAN also supports an alternate masking scheme with only three mask registers (RGXMASK,
RX14MASK, and RX15MASK) for backwards compatibility. This alternate masking scheme is enabled
when the BCC bit in the MCR Register is negated.
18.4.6 Data coherence
In order to maintain data coherency and proper FlexCAN operation, the CPU must obey the rules described
in Transmit process and Section 18.4.4, Receive process. Any form of CPU accessing an MB structure
within FlexCAN other than those specified may cause FlexCAN to behave in an unpredictable way.
18.4.6.1 Transmission abort mechanism
The abort mechanism provides a safe way to request the abortion of a pending transmission. A feedback
mechanism is provided to inform the CPU if the transmission was aborted or if the frame could not be
aborted and was transmitted instead. In order to maintain backwards compatibility, the abort mechanism
must be explicitly enabled by asserting the AEN bit in the MCR.
In order to abort a transmission, the CPU must write a specific abort code (1001) to the Code field of the
Control and Status word. When the abort mechanism is enabled, the active MBs configured as
transmission must be aborted first and then they may be updated. If the abort code is written to an MB that
is currently being transmitted, or to an MB that was already loaded into the SMB for transmission, the
write operation is blocked and the MB is not deactivated, but the abort request is captured and kept pending
until one of the following conditions is satisfied:
• The module loses the bus arbitration.
• There is an error during the transmission.
• The module is put into Freeze mode.
If none of these conditions is reached, then the MB is transmitted correctly, the interrupt flag is set in the
interrupt flag registers (IFRL, IFRH), and an interrupt to the CPU is generated (if enabled). The abort
request is automatically cleared when the interrupt flag is set. On the other hand, if one of the above
conditions is reached, the frame is not transmitted—therefore the abort code is written into the Code field,
the interrupt flag is set in the interrupt flag registers (IFRL, IFRH), and an interrupt is (optionally)
generated to the CPU.
If the CPU writes the abort code before the transmission begins internally, then the write operation is not
blocked—therefore the MB is updated and no interrupt flag is set. In this way the CPU just needs to read
the abort code to make sure the active MB was deactivated. Although the AEN bit is asserted and the CPU
wrote the abort code, in this case the MB is deactivated and not aborted, because the transmission did not
start yet. One MB is only aborted when the abort request is captured and kept pending until one of the
previous conditions is satisfied.
The abort procedure can be summarized as follows:
• CPU writes 1001 into the code field of the Control and Status word.
• CPU reads the CODE field and compares it to the value that was written.
• If the CODE field that was read is different from the value that was written, the CPU must read the
corresponding interrupt flag to check if the frame was transmitted or is currently being transmitted.
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