Overview
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 51
Additional notes on low-power operation:
• Fast wakeup using the on-chip 16 MHz internal RC oscillator allows rapid execution from RAM
on exit from low-power modes
• The 16 MHz internal RC oscillator supports low-speed code execution and clocking of peripherals
when it is selected as the system clock and can also be used as the PLL input clock source to
provide fast startup, without external oscillator delay
• MPC5606S devices include an internal voltage regulator that includes the following features:
— Regulates input to generate all internal supplies
— Manages power gating
— Low-power regulators support operation when in Stop and Standby modes to minimize power
consumption
— Startup on-chip regulators in <50 s for rapid exit of Stop and Standby modes
— Low-voltage detection on main supply and 1.2 V regulated supplies
1.5.2 e200z0h core processor
The e200z0h processor is similar to other processors in the e200zx series, but supports only the VLE
instruction set and does not include the signal processing extension for DSP applications or a floating point
unit.
The e200z0h has all the features of the e200z0 plus:
• Branch acceleration using Branch Target Buffer (BTB)
• Supports independent instruction and data accesses to different memory subsystems, such as
SRAM and flash memory via independent Instruction and Data BIUs
The e200z0h processor uses a four stage in-order pipeline for instruction execution.
1. The Instruction Fetch (stage 1)
2. Instruction Decode/Register file Read/Effective Address Calculation (stage 2)
3. Execute/Memory Access (stage 3)
4. Register Writeback (stage 4)
These stages operate in an overlapped fashion, allowing single clock instruction execution for most
instructions.
The integer execution unit consists of:
• 32-bit Arithmetic Unit (AU)
5
A high level summary of some key durations that need to be considered when recovering from low-power modes.
This does not account for all durations at wakeup. Other delays will be necessary to consider, including but not
limited to the external supply startup time.
IRC wakeup time must not be added to the overall wakeup time as it starts in parallel with the VREG.
All other wakeup times must be added to determine the total startup time.
6
This is the startup of the regulator that happens after the 5 V has reached beyond its POR range. If the external
supply ramp rate is slow, measure from when VREG has crossed beyond the POR threshold; otherwise, this value
will depend on the ramp rate of the external supply (VDDR).
To Next Page
Loading...
