NXP Semiconductors MPC5606S - Page 52

Overview
MPC5606S Microcontroller Reference Manual, Rev. 7
50 Freescale Semiconductor
Table 1-3 summarizes the operating modes of MPC5606S devices.
Table 1-3. Operating mode summary
1
1
Table Key:
On—Powered and clocked
OP—Optionally configurable to be enabled or disabled (clock gated)
CG—Clock Gated, Powered but clock stopped
Off—Powered off and clock gated
FP—VREG Full Performance mode
LP—VREG low-power mode, reduced output capability of VREG but lower power consumption
Var—Variable duration, based on the required reconfiguration and execution clock speed
BAM—Boot Assist Module Software and Hardware used for device startup and configuration
Operating modes: Run Halt Stop Standby POR
SoC features Core On CG CG Off Off —
Peripherals OP OP CG Off
2
2
The LCD can optionally be kept running while the device is in Standby mode.
Off —
Flash memory OP OP CG Off Off —
SRAM On On CG CG
3
3
All of the RAM content is retained, but not accessible in Standby mode.
8 KB
4
4
8 KB of the RAM content is retained, but not accessible in Standby mode.
—
Graphics RAM On On CG Off Off —
Clock sources Main PLL OP OP CG Off Off —
Auxiliary PLL OP OP CG Off Off —
16 MHz IRC On On OP OP OP —
FXOSC OP OP OP OP OP —
128 kHz IRC On On On On On —
32 KHz XOSC OP OP OP OP OP —
Periodic wakeup — OP OP OP OP —
Wakeup input — OP OP OP OP —
VREG mode FP FP LP LP LP —
Wakeup times
5
VREG startup — — 50 s 250 µs 250 µs 250 µs
6
IRC wakeup — — 4 µs 4 µs 8 µs 8 µs
Flash memory
recovery
— — 20 µs 100 µs 100 µs 100 µs
OSC stabilization — — 1 ms 1 ms 1 ms 1 ms
PLL lock — — 200 µs 200 µs 200 µs 200 µs
S/W reconfig — — — Var Var —
Mode switch over — 200.69 µs 24 µs 28 µs 28 µs BAM