Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1047
30.5.2.10.2 Transmit FIFO Fill Interrupt or DMA Request
The Transmit FIFO Fill Request indicates that the TX FIFO is not full. The Transmit FIFO Fill Request is
generated when the number of entries in the TX FIFO is less than the maximum number of possible entries,
and the TFFF_RE bit in the QSPI_SPIRSER is asserted. The TFFF_DIRS bit in the QSPI_SPIRSER
selects whether a DMA request or an interrupt request is generated.
30.5.2.10.3 Transfer Complete Interrupt Request
The Transfer Complete Request indicates the end of the transfer of a serial frame. The Transfer Complete
Request is generated at the end of each frame transfer when the TCF_RE bit is set in the QSPI_SPIRSER.
30.5.2.10.4 Transmit FIFO Underrun Interrupt Request
The Transmit FIFO Underrun Request indicates that an underrun condition in the TX FIFO has occurred.
The transmit underrun condition is detected only in SPI Slave mode. The TFUF bit is set when the TX
FIFO is empty, and a transfer is initiated from an external SPI master. If the TFUF bit is set while the
TFUF_RE bit in the QSPI_SPIRSER is asserted, an interrupt request is generated.
30.5.2.10.5 RX FIFO Drain Interrupt or DMA Request
The RX FIFO Drain Request indicates that the RX FIFO is not empty. The RX FIFO Drain Request is
generated when the number of entries in the RX FIFO is not zero, and the RFDF_RE bit in the
QSPI_SPIRSER is asserted. The RFDF_DIRS bit in the QSPI_SPIRSER selects whether a DMA request
or an interrupt request is generated.
30.5.2.10.6 RX FIFO Overflow Interrupt Request
The RX FIFO Overflow Request indicates that an overflow condition in the RX FIFO has occurred. A RX
FIFO Overflow request is generated when RX FIFO and shift register are full and a transfer is initiated.
The RFOF_RE bit in the QSPI_SPIRSER must be set for the interrupt request to be generated.
Depending on the state of the ROOE bit in the QSPI_MCR, the data from the transfer that generated the
overflow is either ignored or shifted into the shift register. If the ROOE bit is set, the incoming data is
shifted into the shift register. If the ROOE bit is negated, the incoming data is ignored.
30.5.3 SFM (Serial Flash) mode
This mode is used to allow communication with an external serial flash device. Compared to the standard
SPI protocol, this communication method uses up to 4 bidirectional data lines operating at high data rates.
The communication to the external serial flash device consists of an instruction code and optional address,
mode, dummy and data transfers. All operations to the external serial flash device may use only instruction
codes listed in Section 30.7, Serial Flash Devices.
Note that all the information given in this paragraph is applicable only if the QSPI_MCR[QMODE] bit is
set.
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