Stepper Stall Detect (SSD)
MPC5606S Microcontroller Reference Manual, Rev. 7
1166 Freescale Semiconductor
36.4 Functional description
For all the descriptions given here it is assumed that the SSD block has gained exclusive control of the SM
coils and the analog block is enabled appropriately.
36.4.1 Main building blocks of the SSD
The functional description given in this chapter deals with the main functional blocks. It concentrates on
the description of the implemented functionality. Refer to Figure 36-1 for details.
36.4.1.1 Analog block
An overview of the analog block of the SSD block is given in Figure 36-9 below. Additionally the most
important sub blocks of the digital part which are connected to the analog blocks are shown in order to
clarify the joint operation of the analog block and the digital part.
2–0
ACDIV
Accumulator Sample Clock Divider Select. The accumulator sample clock is derived from the bus
clock according to the formula
<accumulator sample clock> = <bus clock> / (8 * 2
ACDIV
)
According to this formula the divider factors are:
000 8
001 16
010 32
011 64
100 128
101 256
110 512
111 1024
The first ITGACC register update occurs when (8 * 2
ACDIV
) bus clocks have expired after the ITGST
bit has been set by the SSD block.
Table 36-9. PRESCALE Register field description (continued)
Field Description
To Next Page
Loading...
