NXP Semiconductors MPC5606S - Interrupt Mask Register (ME_IM)

Mode Entry Module (MC_ME)
MPC5606S Microcontroller Reference Manual, Rev. 7
918 Freescale Semiconductor
25.3.2.5 Interrupt Mask Register (ME_IM)
This register controls whether an event generates an interrupt or not.
Address 0xC3FD_C010 Access: Supervisor read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0
M_ICONF
M_IMODE
M_SAFE
M_MTC
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 25-6. Interrupt Mask Register (ME_IM)
Table 25-8. Interrupt Mask Register (ME_IM) field descriptions
Field Description
M_ICONF Invalid mode configuration interrupt mask
0 Invalid mode interrupt is masked
1 Invalid mode interrupt is enabled
M_IMODE Invalid mode interrupt mask
0 Invalid mode interrupt is masked
1 Invalid mode interrupt is enabled
M_SAFE Safe mode interrupt mask
0 Safe mode interrupt is masked
1 Safe mode interrupt is enabled
M_MTC Mode transition complete interrupt mask
0 Mode transition complete interrupt is masked
1 Mode transition complete interrupt is enabled