NXP Semiconductors MPC5606S - User Test 1 Register (UT1)

Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
618 Freescale Semiconductor
17.3.6.12 User Test 1 register (UT1)
The User Test 1 Register allows to enable the checks on the ECC logic related to the 32 LSB of the Double
Word.
The User Test 1 Register is not accessible whenever MCR.DONE or UT0.AID are low: reading returns
indeterminate data while writing has no effect.
17.3.6.13 User Test 2 register (UT2)
The User Test 2 Register allows to enable the checks on the ECC logic related to the 32 MSB of the Double
Word.
The User Test 2 Register is not accessible whenever MCR.DONE or UT0.AID are low: reading returns
indeterminate data while writing has no effect.
Address Offset: 0x00040 Reset value: 0x00000000
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DAI31 DAI30 DAI29 DAI28 DAI27 DAI26 DAI25 DAI24 DAI23 DAI22 DAI21 DAI20 DAI19 DAI18 DAI17 DAI16
rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
DAI15 DAI14 DAI13 DAI12 DAI11 DAI10 DAI09 DAI08 DAI07 DAI06 DAI05 DAI04 DAI03 DAI02 DAI01 DAI00
rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
Figure 17-35. User Test 1 register (UT1)
Table 17-52. UT1 field descriptions
Field Description
0:31 DAI31-00: Data Array Input 31-0 (Read/Write)
These bits represent the input of even word of ECC logic used in the ECC Logic Check. The DAI31-00
correspond to the 32 array bits representing Word 0 within the double word.
0: The array bit is forced at 0.
1: The array bit is forced at 1.
Address Offset: 0x00044 Reset value: 0x00000000
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DAI63 DAI62 DAI61 DAI60 DAI59 DAI58 DAI57 DAI56 DAI55 DAI54 DAI53 DAI52 DAI51 DAI50 DAI49 DAI48
rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
DAI47 DAI46 DAI45 DAI44 DAI43 DAI42 DAI41 DAI40 DAI39 DAI38 DAI37 DAI36 DAI35 DAI34 DAI33 DAI32
rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
Figure 17-36. User Test 2 register (UT2)