Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 617
26 MRE: Margin Read Enable (Read/Write)
MRE enables margin reads to be done. This bit, combined with MRV, enables regular user mode reads to
be replaced by margin reads.
This bit is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data
while writing has no effect.
0: Margin reads are not enabled, all reads are User mode reads.
1: Margin reads are enabled.
27 MRV: Margin Read Value (Read/Write)
If MRE is high, MRV selects the margin level that is being checked. Margin can be checked to an erased
level (MRV=1) or to a programmed level (MRV=0).
This bit is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data
while writing has no effect.
0: Zero’s (programmed) margin reads are requested (if MRE=1).
1: One’s (erased) margin reads are requested (if MRE=1).
28 EIE: ECC data Input Enable (Read/Write)
EIE enables the ECC Logic Check operation to be done.
This bit is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data
while writing has no effect.
0: ECC Logic Check is not enabled.
1: ECC Logic Check is enabled.
29 AIS: Array Integrity Sequence (Read/Write)
AIS determines the address sequence to be used during array integrity checks or Margin mode.
The default sequence (AIS=0) is meant to replicate sequences normal user code follows, and thoroughly
checks the read propagation paths. This sequence is proprietary.
The alternative sequence (AIS=1) is just logically sequential.
It should be noted that the time to run a sequential sequence is significantly shorter than the time to run
the proprietary sequence. Only the Sequential mode is allowed in Margin mode.
This bit is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data
while writing has no effect.
0: Array Integrity sequence is proprietary sequence.
1: Array Integrity sequence or Margin mode sequence is sequential.
31 AIE: Array Integrity Enable (Read/Write)
AIE set to 1 starts the Array Integrity Check done on all selected and unlocked blocks.
The pattern is selected by AIS, and the MISR (UMISR0-4) can be checked after the operation is complete,
to determine if a correct signature is obtained.
AIE can be set only if MCR.ERS, MCR.PGM and MCR.EHV are all low.
0: Array Integrity Checks, Margin mode, and ECC Logic Checks are not enabled.
1: Array Integrity Checks, Margin mode, and ECC Logic Checks are enabled.
31 AID: Array Integrity Done (Read Only)
AID will be cleared upon an Array Integrity Check being enabled (to signify the operation is on-going).
Once completed, AID will be set to indicate that the Array Integrity Check is complete. At this time the
MISR (UMISR0-4) can be checked.
0: Array Integrity Check is on-going.
1: Array Integrity Check is done.
Table 17-51. UT0 field descriptions (continued)
Field Description
To Next Page
Loading...
