NXP Semiconductors MPC5606S - Chapter 41; NMI Configuration Register (NCR)

Wakeup Unit (WKPU)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1241
41.4.2.2 NMI Configuration Register (NCR)
This register holds the configuration bits for the non-maskable interrupt settings.
Table 41-3. NSR field descriptions
Field Description
0
NIF
NMI Status Flag
This flag can be cleared only by writing a 1. Writing a 0 has no effect. If enabled (NREE or NFEE set),
NIF causes an interrupt request.
0 No event has occurred on the pad
1 An event as defined by NREE and NFEE has occurred
1
NOVF
NMI Overrun Status Flag
This flag can be cleared only by writing a 1. Writing a 0 has no effect. It will be a copy of the current
NIF value whenever an NMI event occurs, thereby indicating to the software that an NMI occurred
while the last one was not yet serviced. If enabled (NREE or NFEE set), NOVF causes an interrupt
request.
0 No overrun has occurred on NMI input
1 An overrun has occurred on NMI input
Address: Base + 0x0008 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
NLO
CK
NDSS
NWR
E
0
NRE
E
NFE
E
NFE
0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 41-3. NMI Configuration Register (NCR)
Table 41-4. NCR field descriptions
Field Description
0
NLOCK
NMI Configuration Lock Register
Writing a 1 to this bit locks the configuration for the NMI until it is unlocked by a system reset. Writing
a 0 has no effect.
1-2
NDSS
NMI Destination Source Select
00 Non-maskable interrupt
01 Critical interrupt
10 Machine check request
11 Reserved—no NMI, critical interrupt, or machine check request generated
3
NWRE[x]
NMI Wakeup Request Enable
0 System wakeup requests from the corresponding NIF bit are disabled
1 A set NIF bit or set NOVF bit causes a system wakeup request
5
NREE
NMI Rising-edge Events Enable
0 Rising-edge event is disabled
1 Rising-edge event is enabled