Stepper Stall Detect (SSD)
MPC5606S Microcontroller Reference Manual, Rev. 7
1162 Freescale Semiconductor
36.3.2.2 Interrupt Enable and Flag Register (IRQ)
Figure 36-3 below describes the fields of the interrupt enable and flag (IRQ) register:
The function of the IRQ register bits is shown in Table 36-4.
8
RTZE
Return to Zero Enable. This is in fact the enable bit of the SSD logic to take over control of the
SM coils
1
.
1 Control of the SM coils by the SSD block is enabled.
0 Control of the SM coils by the SSD block is disabled.
6
BLNST
Blanking Status. Refer to Section 36.1.3.2, Normal mode, for details.
1 The SSD block is currently in the blanking phase of an ongoing BIS.
0 The SSD block is not in the blanking phase of an ongoing BIS.
5
ITGST
Integration Status. Refer to Section 36.1.3.2, Normal mode, for details.
1 The SSD block is currently in the integration phase of an ongoing BIS.
0 The SSD block is not in the integration phase of an ongoing BIS.
1
SDCPU
Sigma-Delta modulator Power Up. Setting this bit enables the analog block of the SSD and
enables the clocking of the port control logic of the digital part.
1 Analog block of the SSD is enabled.
0 Analog block of the SSD is not enabled
0 Reserved
1
The application must switch off any other blocks possibly interfering with port control of the SSD block.
Offset 0x02 Access: User read/write
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BLNI
F
ITGI
F
0 0 0 0 0
ACO
VIF
BLNI
E
ITGI
E
0 0 0 0 0
ACO
VIE
W w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 36-3. SSD Interrupt Flag and Enable Register (IRQ)
Table 36-4. IRQ Register field description
Field Description
15
BLNIF
Blanking expired Interrupt Flag.
1 This flag is set when the BIS blanking phase has expired.
0 No such event.
14
ITGIF
Integration expired Interrupt Flag.
1 This flag is set when the BIS integration phase has expired.
0 No such event.
8
ACOVIF
Accumulator Overflow Interrupt Flag.
1 This flag is set when during the BIS integration phase the integration logic attempted either to increment
the ITGACC register above 0x7FFF or to decrement it below 0x8000.
0 No such event.
Table 36-3. CONTROL Register field description (continued)
Field Description
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