NXP Semiconductors MPC5606S - Control Descriptor L0_4 Register

Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
356 Freescale Semiconductor
Figure 12-5. CtrlDescL0_3 Register
12.3.4.4 Control Descriptor L0_4 Register
Figure 12-6 represents the control descriptor L0_4 register. This register controls various graphics options
and whether the layer is enabled.
Offset:
0x008 (CtrlDescL0_3)
0x024 (CtrlDescL1_3)
0x040 (CtrlDescL2_3)
0x05C (CtrlDescL3_3)
0x078 (CtrlDescL4_3)
0x094 (CtrlDescL5_3)
0x0b0 (CtrlDescL6_3)
0x0CC (CtrlDescL7_3)
0x0E8 (CtrlDescL8_3)
0x104 (CtrlDescL9_3)
0x120 (CtrlDescL10_3)
0x13C (CtrlDescL11_3)
0x158 (CtrlDescL12_3)
0x174 (CtrlDescL13_3)
0x18C (CtrlDescL14_3)
0x1AC (CtrlDescL15_3) Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ADDR[0:15]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ADDR16:31]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 12-7. CtrlDescL0_3 field descriptions
Field Description
0–31
ADDR
Address of layer data in the memory. The address programmed should be 32-bit aligned.