Inter-Integrated Circuit Bus Controller Module (I
2
C)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 743
20.5.2.2 Slave Address Transmission
The first byte of data transfer immediately after the START signal is the slave address transmitted by the
master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired
direction of data transfer.
1 = Read transfer—the slave transmits data to the master
0 = Write transfer—the master transmits data to the slave
Only the slave with a calling address that matches the one transmitted by the master will respond by
sending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see Figure 20-10).
No two slaves in the system may have the same address. If the I
2
C Bus is master, it must not transmit an
address that is equal to its own slave address. The I
2
C Bus cannot be master and slave at the same time.
However, if arbitration is lost during an address cycle the I
2
C Bus will revert to Slave mode and operate
correctly, even if it is being addressed by another master.
20.5.2.3 Data Transfer
Once successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction
specified by the R/W bit sent by the calling master.
All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address
information for the slave device.
Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while
SCL is high as shown in Figure 20-10. There is one clock pulse on SCL for each data bit, the MSB being
transferred first. Each data byte must be followed by an acknowledge bit, which is signaled from the
receiving device by pulling the SDA low at the ninth clock. Therefore, one complete data byte transfer
needs nine clock pulses.
If the slave receiver does not acknowledge the master, the SDA line must be left high by the slave. The
master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to
commence a new calling.
If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means 'end
of data' to the slave, so the slave releases the SDA line for the master to generate a stop or START signal.
20.5.2.4 Stop Signal
The master can terminate the communication by generating a stop signal to free the bus. However, the
master may generate a START signal followed by a calling command without generating a stop signal first.
This is called repeated START. A stop signal is defined as a low-to-high transition of SDA while SCL is
at logical “1” (see Figure 20-10).
The master can generate a stop even if the slave has generated an acknowledge, at which point the slave
must release the bus.
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