Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
236 Freescale Semiconductor
9.1.6 Unified Channel block
Figure 9-2 shows the block diagram of Unified Channel block as it is implemented in this device.
Figure 9-2. Unified Channel block
9.1.6.1 Channel mode selection
The following is a portion of eMIOS200 UC Control Register (EMIOSC[n]). Please see Section 9.4.2.8,
eMIOS200 UC Control Register (EMIOSC[n]).
Counter bus
BSL[0:1]
select
Internal
counter
Prescaler
Comparator A
(with zero detection)
Comparator B
FSM
ODISSL[0:1]
EDPOL
ODIS
UCOUT
IF[0:3]
ipp_ind_mts_uc[n]
UCPRE[0:1] UCPREN
Internal counter clockSee note 1
Counter bus [A]
Counter bus [B], [C] or [D]
EDSEL
Register B1
Register B2
Edge detect
EN
Register A1
Register A2
EN
Register
FORCMA
MODE[0:6]
UPDATE
Output disable
B
Register
A
To register ATo internal counter To register B
control bus
IIB
RQBRWCB
UCIN
FCK
Output flip-flop
See note 2
Prgm. filter
ipp_obe_mts_uc[n]
mts_flag_out[n]
ipp_do_mts_uc[n]
Unified channel
Notes:
1.
See figure 1-1 to check how the counter buses are driven.
2.
Goes to the FSM of the UC[n-1]. These signals are used for QDEC mode.
FLAG
FORCMB
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