NXP Semiconductors MPC5606S - Register Map

Register Map
MPC5606S Microcontroller Reference Manual, Rev. 7
1298 Freescale Semiconductor
MPU RGD Alternate Access Control 15 MPU_RGDAAC15 32-bit Base + 0x083C
Reserved — — Base +
(0x0840–0x3FFF)
SWT 0 Section 4.2.5, Memory map and register description 0xFFF3_8000
Control Register SWT_CR 32-bit Base + 0x0000
SWT Interrupt Register SWT_IR 32-bit Base + 0x0004
SWT Timeout Register SWT_TO 32-bit Base + 0x0008
SWT Window Register SWT_WN 32-bit Base + 0x000C
SWT Service Register SWT_SR 32-bit Base + 0x0010
SWT Counter Output Register SWT_CO 32-bit Base + 0x0014
Reserved — — Base + 0x0018
–0xFFF3_BFFF
STM Section 39.3, Memory map and register definition 0xFFF3_C000
Control Register STM_CR 32-bit Base + 0x0000
STM Count Register STM_CNT 32-bit Base + 0x0004
Reserved — — Base +
(0x0008–0x000F)
STM Channel 0 Control Register STM_CCR0 32-bit Base + 0x0010
STM Channel 0 Interrupt Register STM_CIR0 32-bit Base + 0x0014
STM Channel 0 Compare Register STM_CMP0 32-bit Base + 0x0018
Reserved — — Base +
(0x001C–0x001F)
STM Channel 1 Control Register STM_CCR1 32-bit Base + 0x0020
STM Channel 1 Interrupt Register STM_CIR1 32-bit Base + 0x0024
STM Channel 1 Compare Register STM_CMP1 32-bit Base + 0x0028
Reserved — — Base +
(0x002C–0x002F)
STM Channel 2 Control Register STM_CCR2 32-bit Base + 0x0030
STM Channel 2 Interrupt Register STM_CIR2 32-bit Base + 0x0034
STM Channel 2 Compare Register STM_CMP2 32-bit Base + 0x0038
Reserved — — Base +
(0x003C–0x003F)
STM Channel 3 Control Register STM_CCR3 32-bit Base + 0x0040
STM Channel 3 Interrupt Register STM_CIR3 32-bit Base + 0x0044
Table B-2. Detailed register map (continued)
Register description Register Name
Used
Size
Address