NXP Semiconductors MPC5606S - STM Channel Control Register (Stm_Ccrn)

System Timer Module (STM)
MPC5606S Microcontroller Reference Manual, Rev. 7
1224 Freescale Semiconductor
39.3.2.3 STM Channel Control Register (STM_CCRn)
The STM Channel Control Register (STM_CCRn) has the enable bit for channel n of the timer.
Table 39-4. STM_CCRn field descriptions
39.3.2.4 STM Channel Interrupt Register (STM_CIRn)
The STM Channel Interrupt Register (STM_CIRn) has the interrupt flag for channel n of the timer.
Offset 0x10+0x10*n Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0
0
0 0 0
CEN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 39-3. STM Channel Control Register (STM_CCRn)
Field Description
CEN Channel Enable.
0 The channel is disabled.
1 The channel is enabled.
Offset 0x14+0x10*n Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0
0
0 0 0 CIF
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 39-4. STM Channel Interrupt Register (STM_CIRn)