Power Control Unit (MC_PCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 991
power domain #2 will increase slowly. Once the voltage of power domain #2 is within an operable range,
its clocks are enabled, and its resets are deasserted (startup state).
NOTE
It is possible that, due to a mode change, startup is requested before a power
domain completed its power-down sequence. In this case, the information
in that power domain is lost.
29.4.4.2 Standby mode transition
Standby mode offers the maximum power saving. The level of power saving is software-controllable via
the settings in the PCU_PCONFn registers for power domain #2 onwards. Power domain #0 stays
connected to the power supply while power domain #1 is disconnected from the power supply. Amongst
others power domain #1 contains the platform and the MC_ME. Therefore this mode differs from all other
user/system modes.
Once Standby is entered it can only be left via a system wakeup. On exiting the Standby mode, all power
domains are powered up according to the settings in the PCU_PCONFn registers, and the DRUN mode is
entered. In DRUN mode, at least power domains #0 and #1 are powered.
Figure 29-7 shows an example for a mode transition from Run0 to Standby to DRUN. All power domains
which have PCU_PCONFn.STBY0 cleared will enter power-down phase. In this example only power
domain #1 will be disabled during Standby mode.
When the MC_PCU receives the mode change request to Standby mode it starts the power down phase for
power domain #1. During the power down phase, clocks are disabled and reset is asserted resulting in a
loss of all information for this power domain. Then the power domain is disconnected from the power
supply (power-down state).
Figure 29-7. MC_PCU Events During Power Sequences (Standby mode)
new mode
power-down
RUN0
voltage in
PSTAT.PD1
STANDBY
Notes:
Not drawn to scale; PCONF1.RUN0 = 1; PCONF1.STBY0 = 0
current mode
startup phase
power domain #1
RUN0 STANDBY
DRUN
requested by ME
power-down state
startup state
startup state
phase
Mode set due to reset being asserted to power domain #1
wakeup request
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