FlexCAN
MPC5606S Microcontroller Reference Manual, Rev. 7
688 Freescale Semiconductor
18.3.4.5 Rx 14 Mask (RX14MASK)
This register is provided for legacy support and for low-cost MCUs that do not have the individual masking
per Message Buffer feature. For MCUs supporting individual masks per MB, setting the BCC bit in MCR
causes the RX14MASK Register to have no effect on the module operation.
RX14MASK is used as acceptance mask for the identifier in Message Buffer 14. When the FEN bit in
MCR is set (FIFO enabled), the RXG14MASK also applies to element 6 of the ID filter table. This register
has the same structure as the Rx Global Mask Register. It must be programmed while the module is in
Freeze mode, and must not be modified when the module is transmitting or receiving frames.
• Address offset: 0x14
• Reset value: 0xFFFF_FFFF
See Section 18.3.4.4, Rx Global Mask (RXGMASK) for more information on mask alignment.
18.3.4.6 Rx 15 Mask (RX15MASK)
This register is provided for legacy support and for low-cost MCUs that do not have the individual masking
per Message Buffer feature. For MCUs supporting individual masks per MB, setting the BCC bit in MCR
causes the RX15MASK Register to have no effect on the module operation.
When the BCC bit is negated, RX15MASK is used as acceptance mask for the Identifier in Message Buffer
15. When the FEN bit in MCR is set (FIFO enabled), the RXG14MASK also applies to element 7 of the
ID filter table. This register has the same structure as the Rx Global Mask Register. It must be programmed
while the module is in Freeze mode, and must not be modified when the module is transmitting or
receiving frames.
• Address offset: 0x18
• Reset value: 0xFFFF_FFFF
See Section 18.3.4.4, Rx Global Mask (RXGMASK) for more information on mask alignment.
18.3.4.7 Error Counter Register (ECR)
This register has two 8-bit fields reflecting the value of two FlexCAN error counters: Transmit Error
Counter (Tx_Err_Counter field) and Receive Error Counter (Rx_Err_Counter field). The rules for
increasing and decreasing these counters are described in the CAN protocol and are completely
implemented in the FlexCAN module. Both counters are read-only, except in Freeze mode where they can
be written by the CPU.
Table 18-11. Rx Global Mask Register (RXGMASK) field descriptions
Field Description
0-31
MI31–MI0
Mask Bits
For normal Rx MBs, the mask bits affect the ID filter programmed on the MB. For the Rx FIFO, the
mask bits affect all bits programmed in the filter table (ID, IDE, RTR).
0 the corresponding bit in the filter is “don’t care”
1 The corresponding bit in the filter is checked against the one received
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