FlexCAN
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 689
Writing to the Error Counter Register while in Freeze mode is an indirect operation. The data is first written
to an auxiliary register. Then an internal request/acknowledge procedure across clock domains is executed.
All this is transparent to the user, except for the fact that the data will take some time to be actually written
to the register. If desired, software can poll the register to discover when the data was actually written.
FlexCAN responds to any bus state as described in the protocol, for example, transmit the Error Active or
Error Passive flag, delay its transmission start time (Error Passive), and avoid any influence on the bus
when in Bus Off state. The following are the basic rules for FlexCAN bus state transitions.
• If the value of Tx_Err_Counter or Rx_Err_Counter increases to be greater than or equal to 128, the
FLT_CONF field in the Error and Status Register is updated to reflect the Error Passive state.
• If the FlexCAN state is Error Passive, and either Tx_Err_Counter or Rx_Err_Counter decrements
to a value less than or equal to 127 while the other already satisfies this condition, the FLT_CONF
field in the Error and Status Register is updated to reflect the Error Active state.
• If the value of Tx_Err_Counter increases to be greater than 255, the FLT_CONF field in the Error
and Status Register is updated to reflect the Bus Off state, and an interrupt may be issued. The value
of Tx_Err_Counter is then reset to zero.
• If FlexCAN is in the Bus Off state, then Tx_Err_Counter is cascaded together with another internal
counter to count the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
Tx_Err_Counter is reset to zero and counts in a manner where the internal counter counts 11 such
bits and then wraps around while incrementing the Tx_Err_Counter. When Tx_Err_Counter
reaches the value of 128, the FLT_CONF field in the Error and Status Register is updated to be
Error Active, and both error counters are reset to zero. At any instance of a dominant bit following
a stream of less than 11 consecutive recessive bits, the internal counter resets itself to zero without
affecting the Tx_Err_Counter value.
• If during system startup only one node is operating, then its Tx_Err_Counter increases in each
message it is trying to transmit, as a result of acknowledge errors (indicated by the ACK_ERR bit
in the Error and Status Register). After the transition to the Error Passive state, the Tx_Err_Counter
does not increment anymore by acknowledge errors. Therefore, the device never goes to the Bus
Off state.
• If the Rx_Err_Counter increases to a value greater than 127, it is not incremented further, even if
more errors are detected while being a receiver. At the next successful message reception, the
counter is set to a value between 119 and 127 to resume the Error Active state.
Address: Base + 0x001C Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Rx_Err_Counter Tx_Err_Counter
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 18-9. Error Counter Register (ECR)
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