DMA Channel Mux (DMACHMUX)
MPC5606S Microcontroller Reference Manual, Rev. 7
450 Freescale Semiconductor
• Each channel router can be assigned to one of 48 possible peripheral DMA slots or to one of the
four always-on slots
13.1.3 Modes of operation
The following operation modes are available:
• Disabled mode
In this mode, the DMA channel is disabled. Since disabling and enabling of DMA channels is done
primarily via the DMA configuration registers, this mode is used mainly as the reset state for a
DMA channel in the DMA channel mux. It may also be used to temporarily suspend a DMA
channel while reconfiguration of the system takes place (for example, changing the period of a
DMA trigger).
• Normal mode
In this mode, a DMA source (such as DSPI transmit or DSPI receive for example) is routed directly
to the specified DMA channel. The operation of the DMA Mux in this mode is completely
transparent to the system.
• Periodic Trigger mode
In this mode, a DMA source may only request a DMA transfer (such as when a transmit buffer
becomes empty or a receive buffer becomes full) periodically. Configuration of the period is done
in the registers of the Periodic Interrupt Timer (PIT). This mode is only available for channels 0–4.
13.2 External signal description
13.2.1 Overview
The DMA channel mux has no external pins.
13.3 Memory map and register definition
This section provides a detailed description of all memory-mapped registers in the DMA channel mux.
Table 13-1 shows the memory map for the DMA channel mux. Note that all addresses are offsets; the
absolute address may be computed by adding the specified offset to the base address of the DMA channel
mux.
Table 13-1. Module memory map
Address Use Access Location
Base + 0x00 Channel #0 Configuration (CHCONFIG0) R/W on page 451
Base + 0x01 Channel #1 Configuration (CHCONFIG1) R/W on page 451
.. .. .. ..
Base + 0x#n – 1 Channel #n Configuration (CHCONFIG#n – 1)
1
1
In the table n refers to the number of channels – 1
R/W on page 451
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