Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 631
17.3.8 Error Correction Code (ECC)
The flash memory macrocell provides a method to improve the reliability of the data stored in flash
memory: the usage of an error correction code. The word size is fixed of 64 bits.
At each double word of 64 bits, there are associated 8 ECC bits that are programmed in such a way to
guarantee a Single Error Correction and a Double Error Detection (SEC-DED).
ECC circuitry provides correction of single bit faults and is used to achieve automotive reliability targets.
Some units will experience single bit corrections throughout the life of the product with no impact to
product reliability.
17.3.8.1 ECC algorithm
The flash memory macrocell supports one ECC algorithm: “All 1s No Error”. This algorithm detects as
valid any Double Word read on a just erased sector (all the 72 bits are 1s).
This option allows to perform a Blank Check after a Sector Erase operation.
17.3.8.2 Bit manipulation
The ECC algorithm allows some bit manipulations so that a Double Word can be rewritten several times
without needing an erase of the sector. This allows to use a Double Word to store flags useful for the
Eeprom Emulation.
As an example the ECC algorithm allows to start from an All 1s Double Word value and rewrite whichever
of its four 16-bits Half-Words to an All 0s content by keeping the same ECC value.
Table 17-60 shows a set of Double Words sharing the same ECC value.
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