NXP Semiconductors MPC5606S - User Test 2 Register (UT2)

Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
576 Freescale Semiconductor
17.2.6.17 User Test 2 register (UT2)
The User Test 2 Register allows to enable the checks on the ECC logic related to the 32 MSB of the Double
Word.
The User Test 2 Register is not accessible whenever MCR.DONE or UT0.AID are low: reading returns
indeterminate data while writing has no effect.
17.2.6.18 User Multiple Input Signature Register 0 (UMISR0)
The Multiple Input Signature Register provides a mean to evaluate the Array Integrity.
The User Multiple Input Signature Register 0 represents the bits 31-0 of the whole 144 bits word (2 Double
Words including ECC).
Address Offset: 0x00044 Reset value: 0x00000000
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DAI63 DAI62 DAI61 DAI60 DAI59 DAI58 DAI57 DAI56 DAI55 DAI54 DAI53 DAI52 DAI51 DAI50 DAI49 DAI48
rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
DAI47 DAI46 DAI45 DAI44 DAI43 DAI42 DAI41 DAI40 DAI39 DAI38 DAI37 DAI36 DAI35 DAI34 DAI33 DAI32
rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
Figure 17-15. User Test 2 register (UT2)
Table 17-25. UT2 field descriptions
Field Description
0:31 DAI63-32: Data Array Input 63-32 (Read/Write)
These bits represent the input of odd word of ECC logic used in the ECC Logic Check. The DAI63-32
correspond to the 32 array bits representing Word 1 within the double word.
0: The array bit is forced at 0.
1: The array bit is forced at 1.
Address Offset: 0x00048 Reset value: 0x00000000
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MS03
1
MS03
0
MS02
9
MS02
8
MS02
7
MS02
6
MS02
5
MS02
4
MS02
3
MS02
2
MS02
1
MS02
0
MS01
9
MS01
8
MS01
7
MS01
6
rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
MS01
5
MS01
4
MS01
3
MS01
2
MS01
1
MS01
0
MS00
9
MS00
8
MS00
7
MS00
6
MS00
5
MS00
4
MS00
3
MS00
2
MS00
1
MS00
0
rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
Figure 17-16. User Multiple Input Signature Register 0 (UMISR0)