NXP Semiconductors MPC5606S - DMA Interrupt Request (DMAINTH, DMAINTL) Registers

Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
490 Freescale Semiconductor
15.3.1.13 DMA Interrupt Request (DMAINTH, DMAINTL) registers
The DMAINT{H,L} registers provide a bit map for the implemented channels {16,32,64} signaling the
presence of an interrupt request for each channel. DMAINTH supports channels 63–32, while DMAINTL
covers channels 31–00. The DMA engine signals the occurrence of a programmed interrupt upon the
completion of a data transfer as defined in the transfer control descriptor by setting the appropriate bit in
this register. The outputs of this register are directly routed to the platform’s interrupt controller. During
the execution of the interrupt service routine associated with any given channel, it is software’s
responsibility to clear the appropriate bit, negating the interrupt request. Typically, a write to the
DMACINT register in the interrupt service routine is used for this purpose.
The state of any given channel’s interrupt request is directly affected by writes to this register; it is also
affected by writes to the DMACINT register. On writes to the DMAINT, a one in any bit position clears
the corresponding channel’s interrupt request. A zero in any bit position has no effect on the corresponding
channel’s current interrupt status. The DMACINT register is provided so the interrupt request for a single
channel can easily be cleared without the need to perform a read-modify-write sequence to the
DMAINT{H,L} registers. See Figure 15-16, Figure 15-17, and Table 15-14 for the DMAINT definition.
Address: Base + 0x001F Access: User write-only
0 1 2 3 4 5 6 7
R 0 0 0 0 0 0 0 0
W NOP CDNE[0:6]
Reset 0 0 0 0 0 0 0 0
Figure 15-15. DMA Clear DONE Status (DMACDNE) register
Table 15-13. DMA Clear DONE Status (DMACDNE) field descriptions
Name Description
NOP No Operation
0 Normal operation.
1 No operation, ignore bits 6-0
CDNE[0:6] Clear DONE Status Bit
0–63 Clear the corresponding channel’s DONE bit 64-127 Clear all TCD DONE bits
Address: Base + 0x0020 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
INT
63
INT
62
INT
61
INT
60
INT
59
INT
58
INT
57
INT
56
INT
55
INT
54
INT
53
INT
52
INT
51
INT
50
INT
49
INT
48
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
INT
47
INT
46
INT
45
INT
44
INT
43
INT
42
INT
41
INT
40
INT
39
INT
38
INT
37
INT
36
INT
35
INT
34
INT
33
INT
32
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 15-16. DMA Interrupt Request High (DMAINTH) register