LIN Controller (LINFlex)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 845
23.7.2.4 LIN error status register (LINESR)
Address: Base + 0x000C Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R SZF OCF BEF CEF
SFEF
BDEF
IDPEF
FEF BOF 0 0 0 0 0 0 NF
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 23-10. LIN error status register (LINESR)
Table 23-9. LINESR field descriptions
Field Description
0:15 Reserved
SZF
16
Stuck at Zero Flag
This bit is set by hardware when the bus is dominant for more than a 100-bit time. If the dominant
state continues, SZF flag is set again after 87-bit time. It is cleared by software.
OCF
17
Output Compare Flag
0 No output compare event occurred
1 The content of the counter has matched the content of OC1[0:7] or OC2[0:7] in LINOCR. If this
bit is set and IOT bit in LINTCSR is set, LINFlex moves to Idle state.
If LTOM bit in LINTCSR is set, then OCF is cleared by hardware in Initialization mode. If LTOM bit is
cleared, then OCF maintains its status whatever the mode is.
BEF
18
Bit Error Flag
This bit is set by hardware and indicates to the software that LINFlex has detected a bit error. This
error can occur during response field transmission (Slave and Master modes) or during header
transmission (in Master mode).
This bit is cleared by software.
CEF
19
Checksum Error Flag
This bit is set by hardware and indicates that the received checksum does not match the hardware
calculated checksum.
This bit is cleared by software.
Note: This bit is never set if CCD or CFD bit in LINCR1 is set.
SFEF
20
Synch Field Error Flag
This bit is set by hardware and indicates that a Synch Field error occurred (inconsistent Synch Field).
BDEF
21
Break Delimiter Error Flag
This bit is set by hardware and indicates that the received Break Delimiter is too short (less than one
bit time).
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