Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
596 Freescale Semiconductor
17.3.4 Functional description
17.3.4.1 Macrocell structure
The flash module is addressable by word (32 bits) or double word (64 bits) for program, and page (128
bits) for read. Reads done to the flash always return 128 bits, although read page buffering may be done
in the platform BIU.
Each read of the flash module retrieves a page, or four consecutive words (128 bits) of information. The
address for each word retrieved within a page differ from the other addresses in the page only by address
bits (3:2).
The flash module supports fault tolerance through Error Correction Code (ECC) and/or error detection.
The ECC implemented within the flash module will correct single bit failures and detect double bit
failures.
The flash module uses an embedded hardware algorithm implemented in the Memory Interface to program
and erase the flash core.
Control logic that works with the software block enables, and software lock mechanisms, is included in
the embedded hardware algorithm to guard against accidental program/erase.
The hardware algorithm perform the steps necessary to ensure that the storage elements are programmed
and erased with sufficient margin to guarantee data integrity and reliability.
A programmed bit in the flash module reads as logic level 0 (or low).
An erased bit in the flash module reads as logic level 1 (or high).
Program and erase of the flash module requires multiple system clock cycles to complete.
The erase sequence may be suspended.
The program and erase sequences may be aborted.
17.3.4.2 Flash module sectorization
The data flash module supports 64 KB of user memory, plus 16 KB of test memory (a portion of which is
one-time programmable by the user).
The flash module is composed by a single Bank (Bank 0): Read-While-Modify is not supported.
Bank 0 of the 80 KB flash memory macrocell is divided in four sectors. Bank 0 contains also a reserved
sector named Test flash in which some One Time Programmable user data are stored.
The sectorization of the 80 KB Matrix Module is shown in Table 17-38.
Table 17-38. 80 KB flash module sectorization
Bank Sector Addresses Size Address Space
B1 B1F0 0x00800000 to 0x00803FFF 16 KB Low Address Space
B1 B1F1 0x00804000 to 0x00807FFF 16 KB Low Address Space
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