NXP Semiconductors MPC5606S - Peripheral Status Register 0 (ME_PS0)

Mode Entry Module (MC_ME)
MPC5606S Microcontroller Reference Manual, Rev. 7
928 Freescale Semiconductor
25.3.2.16 Peripheral Status Register 0 (ME_PS0)
This register provides the status of the peripherals. Please refer to Table 25-12 for details.
SYSCLK System clock switch control — These bits specify the system clock to be used by the system.
0000 16MHz int. RC osc.
0001 div. 16MHz int. RC osc.
0010 reserved
0011 div. 4-16MHz ext. osc.
0100 primary freq. mod. PLL
0101 reserved
0110 reserved
0111 reserved
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 system clock is disabled
Address 0xC3FD_C060 Access: Supervisor read
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
S_BAM
0 0 0 0 0 0 0
S_DMA_CH_MUX
0 0 0 0 0
S_FlexCAN1 S_FlexCAN0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0 0 0 0
S_QUADSPI
0 0 0
S_QUADSPI
S_DSPI1 S_DSPI0
0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 25-17. Peripheral Status Register 0 (ME_PS0)
Table 25-11. Mode Configuration Registers (ME_<mode>_MC) field descriptions (continued)
Field Description