NXP Semiconductors MPC5606S - Soft Lock POL Register

Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 401
12.3.4.44 Soft Lock POL Register
Figure 12-53 represents the Soft Lock POL Register.
Figure 12-53. Soft Lock POL Register
12.3.4.45 Soft Lock L0_TRANSP Register
Figure 12-54 represents the Soft Lock L0_TRANSP register.
Offset: 0x314 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
SLB_POL
0 0 0 0 0 0 0 0 0 0 0
W
WEN_POL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 12-48. Soft Lock POL Register field descriptions
Field Description
0
WEN_POL
Write Enable for Soft Lock Bit SLB_POL
0 SLB is not modified
1 Value is written to SLB
4
SLB_POL
Soft Lock Bit for SYN_POL Register.
0 Associated protected register is not locked and writeable
1 Associated protected register is locked for write access