Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 431
— CRC_OVERFLOW
— P1_FIFO_HI_FLAG
— P1_FIFO_LO_FLAG
— P2_FIFO_LO_FLAG
— P2_FIFO_HI_FLAG
— P3_FIFO_HI_FLAG
— P3_FIFO_LOW_FLAG
— P4_FIFO_HI_FLAG
— P4_FIFO_LOW_FLAG
—IPM_ERROR
• Parameter error interrupts
—Layer Error
— Signature Calculator Error
— Display Error
— HWC_error
• PDI-related interrupts (pdi_int)
— This includes PDI related interrupts. See Section 12.8.2.7, PDI-related interrupts, for a
description.
When any interrupt occurs, the host can identify which type of interrupt has occurred by reading the
interrupt status register/PDI status register/PARR_ERR status register.
12.6 Register protection
There is a customized register protection scheme on the DCU that is different to the protection scheme
implemented elsewhere on the MCU. The scheme provides a mechanism to protect certain registers in the
DCU from being written.
12.6.1 Operation of scheme
The register protection scheme provides a two-step protection scheme for the protected register.
Firstly, each register has an associated soft lock bit (SLB) that prevents further writes to the register when
it is set. Each SLB has a corresponding write enable (WEN) bit that must be set in the same write operation
as the SLB. The SLB can be set or cleared by writing a '1' or '0' to it while its WEN bit is set. The SLB bits
are in the Soft Lock Registers L0 and L1, DISP_SIZE, HSYNC/VSYNC_PARA, POL, L0_TRANSP and
L1_TRANSP registers.
Secondly, there is a hard lock bit (HLB) in the Global Protection Register which prevents all changes to
soft lock bits. The HLB can only be cleared by a system reset.
If a write is made to a register whose SLB is set then a transfer error occurs that generates an IVOR2
exception on the CPU. Similarly if the HLB is set then any write to the SLB registers causes a transfer
error.
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