Stepper Stall Detect (SSD)
MPC5606S Microcontroller Reference Manual, Rev. 7
1164 Freescale Semiconductor
36.3.2.5 Blanking Counter Load Register (BLNCNTLD)
Figure 36-6 below describes the fields of the blanking counter load (BLNCNTLD) register:
The function of the BLNCNTLD register bits is shown in Table 36-7.
36.3.2.6 Integration Counter Load Register (ITGCNTLD)
Figure 36-7 below describes the fields of the integration counter load (ITGCNTLD) register:
The function of the ITGCNTLD register bits is shown in Table 36-8.
Table 36-6. DCNT Register field description
Field Description
15–0
DCNT
Down Counter value. This register represents the actual value of the down counter in unsigned format.
Refer to the functional description of the integrator for further details.
Offset 0x08 Access: User read/write
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BLNCNTLD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 36-6. SSD Blanking Counter Load Register (BLNCNTLD)
Table 36-7. BLNCNTLD Register field description
Field Description
15–0
BLNCNTLD
Blanking Count Load value. This register is programmed with the number of down counter periods
belonging to the blanking phase of the following BISs. Number format is unsigned. Refer to the
Functional Description of the integrator for further details.
Programming all 0’s into the BLNCNTLD register bits disables blanking completely.
Offset 0x0A Access: User read/write
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ITGCNTLD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 36-7. SSD Integration Counter Load Register (ITGCNTLD)
Table 36-8. ITGCNTLD Register field description
Field Description
15–0
ITGCNTLD
Integration Count Load value. This register is programmed with the number of down counter periods
belonging to the integration phase of the following BISs. Number format is unsigned. Refer to the
functional description of the integrator for further details.
Programming all 0’s into the ITGCNTLD register bits disables integration completely.
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