FlexCAN
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 697
18.4 Functional description
18.4.1 Overview
The FlexCAN module is a CAN protocol engine with a very flexible mailbox system for transmitting and
receiving CAN frames. The mailbox system is composed of a set of up to 64 Message Buffers (MB) that
store configuration and control data, time stamp, message ID, and data (see Section 18.3.2, Message
Buffer structure). The memory corresponding to the first eight MBs can be configured to support a FIFO
reception scheme with a powerful ID filtering mechanism, capable of checking incoming frames against
a table of IDs (up to eight extended IDs or 16 standard IDs or 32 8-bit ID slices), each one with its own
individual mask register. Simultaneous reception through FIFO and mailbox is supported. For mailbox
reception, a matching algorithm makes it possible to store received frames only into MBs that have the
same ID programmed on its ID field. A masking scheme makes it possible to match the ID programmed
on the MB with a range of IDs on received CAN frames. For transmission, an arbitration algorithm decides
the prioritization of MBs to be transmitted based on the message ID (optionally augmented by three local
priority bits) or the MB ordering.
Before proceeding with the functional description, an important concept must be explained. A Message
Buffer is said to be active at a given time if it can participate in the matching and arbitration algorithms
that are happening at that time. An Rx MB with a 0000 code is inactive (refer to Table 18-5). Similarly, a
Tx MB with a 1000 or 1001 code is also inactive (refer to Table 18-6). An MB not programmed with 0000,
1000, or 1001 will be temporarily deactivated (will not participate in the current arbitration or matching
run) when the CPU writes to the Control and Status field of that MB (see
Section 18.4.6.2, Message Buffer
deactivation).
Base + 0x0898 RXIMR6 Base + 0x08D8 RXIMR22
Base + 0x089C RXIMR7 Base + 0x08DC RXIMR23
Base + 0x08A0 RXIMR8 Base + 0x08E0 RXIMR24
Base + 0x08A4 RXIMR9 Base + 0x08E4 RXIMR25
Base + 0x08A8 RXIMR10 Base + 0x08E8 RXIMR26
Base + 0x08AC RXIMR11 Base + 0x08EC RXIMR27
Base + 0x08B0 RXIMR12 Base + 0x08F0 RXIMR28
Base + 0x08B4 RXIMR13 Base + 0x08F4 RXIMR29
Base + 0x08B8 RXIMR14 Base + 0x08F8 RXIMR30
Base + 0x08BC RXIMR15 Base + 0x08FC RXIMR31
Table 18-19. RXIMR0–RXIMR31 addresses (continued)
Address Register Address Register
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