NXP Semiconductors MPC5606S - Register Description

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
242 Freescale Semiconductor
9.4.2 Register description
All control registers are 32 bits wide. This chapter shows the eMIOS200 with 24 Unified Channels and
16-bit wide data registers.
9.4.2.1 eMIOS200 Module Configuration Register (EMIOSMCR)
The EMIOSMCR contains global control bits for the eMIOS200 block.
Address: eMIOS200 base address +0x00 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
MDI
S
FRZ
0 0
GPR
EN
0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
GPRE
0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-5. eMIOS200 Module Configuration Register (EMIOSMCR)
Table 9-9. EMIOSMCR field descriptions
Field Description
MDIS Module Disable
Puts the eMIOS200 in low-power mode. The MDIS bit is used to stop the clock of the block, except
the access to registers EMIOSMCR, EMIOSOUDIS, and EMIOSUCDIS.
0 Clock is running
1 Enter low-power mode
FRZ Freeze
Enable the eMIOS200 to freeze the registers of the Unified Channels when the MCU is stopped by
a debugger. Each Unified Channel should have FREN bit set in order to enter freeze state. While in
Freeze state, the eMIOS200 continues to operate to allow the MCU access to the Unified Channel
registers. The Unified Channel will remain frozen until the FRZ bit is written to zero, or the MCU exits
Debug mode, or the Unified Channel FREN bit is cleared.
0 Exit freeze state
1 Stops Unified Channels operation when in Debug mode and the FREN bit is set in the EMIOSC[n]
register
GPREN Global Prescaler Enable
The GPREN bit enables the prescaler counter.
0 Prescaler disabled (no clock) and prescaler counter is cleared
1 Prescaler enabled
GPRE Global Prescaler
The GPRE[0:7] bits select the clock divider value for the global prescaler, as shown in Table 9-10.