Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1051
arbitrarily. Refer to Section 30.4.3.15, RX Buffer Data Registers 0–14
(QSPI_RBDR0–QSPI_RBDR14), for details.
Note that after clearing the RX Buffer the next entry is written into QSPI_RBDR0. Aside from that
there is no information available about the current positions of the RX Buffer read and write
pointers.
It is not recommended to use this access scheme for subsequent reads of more than 15 data words.
• AHB Buffer data read via memory-mapped access: This kind of access is done by reading one
of the addresses assigned to the external serial flash device within the range given in Table 30-35
under the condition that the data requested are already present in the AHB Buffer or it is currently
read from the serial flash device. If this is not the case a memory-mapped read of the AHB Buffer
is triggered like described above). As long as the requested data are already available in the AHB
Buffer they are provided to the host. The host can read the available data out of the AHB Buffer in
any order.
If the address requested by the current read is the one currently fetched by the QuadSPI module
from the serial flash the execution of the current command remains running with the AHB read
access stalled. As soon as the data from the requested address have been read by the QuadSPI
module the AHB read access is served. So it’s possible to run sequential read from the AHB buffer
at arbitrary speed without the need to monitor any information about the availability of the data.
Nevertheless this access scheme stalls the AHB bus for the time required to read the data from the
serial flash device.
As long as the host restricts its accesses to the data already in the buffer and the data currently
fetched from the serial flash it is possible to run the host read from the AHB Buffer in parallel to
the serial flash read into the AHB Buffer.
30.5.3.4 Byte Ordering of Serial Flash Data
Table 30-45 below gives the byte ordering scheme how the byte oriented data space of the serial flash
device is mapped into the data space of the external serial flash. This scheme is valid for all read and write
operations.
Refer to the individual register descriptions for details like misaligned or partial accesses to the QuadSPI
address space representing serial flash read data.
Table 30-45. Byte Ordering of Serial Flash Data in the QuadSPI Module
Serial Flash Byte Address [1:0]
00 01 10 11
QuadSPI Register Bit Position [31:0]
(32 Bit data width)
[7:0] [15:8] [23:16] [31:24]
Example Data
0x0123_4567
0x01 0x23 0x45 0x67
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