NXP Semiconductors MPC5606S - Emios200 Global FLAG Register (EMIOSGFLAG)

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 243
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9.4.2.2 eMIOS200 Global FLAG Register (EMIOSGFLAG)
The EMIOSGFLAG is a read-only register that groups the FLAG bits from all channels. This organization
improves interrupt handling on simpler devices. Each bit relates to one channel.
The two modules on this device, EMIOS0 and EMIOS1, have different structures for this register as shown
in Figure 9-6 and Figure 9-7.
For Unified Channels these bits are mirrors of the FLAG bits in the EMIOSS[n] register.
Table 9-10. Global Prescaler clock divider
GPRE[0:7] Divide ratio
00000000 1
00000001 2
00000010 3
00000011 4
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11111110 255
11111111 256
Address: eMIOS0 base address +0x04 Access: User read-only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 F23 F22 F21 F20 F19 F18 F17 F16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R F15 F16 F17 F18 F19 F10 F9 F8 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-6. eMIOS200 Global FLAG Register (EMIOSGFLAG) for EMIOS0