NXP Semiconductors MPC5606S - Modes of Operation

Safety
MPC5606S Microcontroller Reference Manual, Rev. 7
112 Freescale Semiconductor
• Once configured, lock bits can be protected from changes
4.1.1.3 Modes of operation
The Register Protection module is operable when the module under protection is operable. For further
details about the availability please see Appendix A, Registers Under Protection.
4.1.2 External signal description
There are no external signals.
4.1.3 Memory map and register description
This section provides a detailed description of the memory map of a module using the Register Protection.
The original 16 KB module memory space is divided into five areas as shown in Figure 4-2.
Figure 4-2. Register protection memory diagram
Area 1 is 6 KB starting at address 0x0000 and holds the normal functional module registers and is
transparent for all read/write operations.
Area 2 is 2 KB starting at address 0x1800 and is a reserved area, that cannot be accessed.
Area 3 is 6 KB starting at address 0x2000 and is a mirror of area 1. A read/write access to these
0x2000
+ X addresses will read/write the register at address X. As a side effect, a write access to address
0x2000
+ X will set the optional Soft Lock Bits for this address X in the same cycle as the register at
address X is written. Not all registers in area 1 need to have protection defined by associated Soft Lock
Module register space
Base + 0x0000
6KB
2 KB Reserved
Mirror module register space
6KB
1.5 KB Lock Bits
with user-defined
Base + 0x1800
Base + 0x2000
Base + 0x3800
soft locking function
512 bytes Configuration
Base + 0x3E00
Base + 0x3FFF
Area 1
Area 2
Area 3
Area 4
Area 5