NXP Semiconductors MPC5606S - Register Descriptions

DMA Channel Mux (DMACHMUX)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 451
All registers are accessible via 8-bit, 16-bit, or 32-bit accesses. However, 16-bit accesses must be aligned
to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. As an example,
CHCONFIG0 through CHCONFIG3 are accessible by a 32-bit read/write to address Base + 0x00, but
performing a 32-bit access to address Base + 0x01 is illegal.
13.3.1 Register descriptions
The following memory-mapped registers are available in the DMA channel mux.
13.3.1.1 Channel configuration registers
Each of the DMA channels can be independently enabled/disabled and associated with one of the DMA
slots (peripheral slots or always-on slots) in the system.
Address: Base + #n Access: User read/write
0 1 2 3 4 5 6 7
R
ENBL TRIG SOURCE
W
Reset 0 0 0 0 0 0 0 0
Figure 13-2. Channel Configuration Registers (CHCONFIG#n)
Table 13-2. CHCONFIGxx field descriptions
Field Description
ENBL DMA Channel Enable. ENBL enables the DMA Channel
0 DMA channel is disabled. 
This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel
enables/disables, which should be used to disable or re-configure a DMA channel.
1 DMA channel is enabled.
TRIG DMA Channel Trigger Enable (for triggered channels only). TRIG enables the periodic trigger
capability for the DMA Channel.
0 Triggering is disabled. 
If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified
source to the DMA channel.
1 Triggering is enabled.
SOURCE DMA Channel Source (slot). SOURCE specifies which DMA source, if any, is routed to a particular
DMA channel. Please check your SoC guide for further details about the peripherals and their slot
numbers.
Table 13-3. Channel and trigger enabling
ENBL TRIG Function Mode
0 X DMA channel is disabled Disabled mode
1 0 DMA channel is enabled with no triggering (transparent) Normal mode
1 1 DMA channel is enabled with triggering Periodic Trigger mode