NXP Semiconductors MPC5606S - Auxiliary Clocks

Clock Description
MPC5606S Microcontroller Reference Manual, Rev. 7
188 Freescale Semiconductor
Figure 8-1. MPC5606S system clock generation
8.2 Auxiliary clocks
This device has four auxiliary clocks configurable using the MC_CGM registers. These auxiliary clocks
allow the associated peripherals to operate at clock speeds independent of the system clock (sys_clk). The
peripherals also use the undivided system clock to synchronously interface with the rest of the device. The
auxiliary clock configuration is as follows:
/1 to /32
OscA
(XOSC)
IRC
Fast
IRC
Slow
System
FMPLL0
FXOSC_clk_divided
FIRC_clk_divided
(64 Mhz)
(eg 8 MHz)
(eg 16 MHz)
sys_clk
Core,
Platform
Watchdog
API/RTC
OscB
(XOSC)
SXOSC_clk
(32 KHz)
SXOSC_clk_divided
SIRC_clk_divided
SIRC_clk_divided
SIRC_clk
FIRC_clk
FXOSC_clk
(via MC_RGM)
CLKOUT
/1, /2, /4, /8
PLL0_Clk
(eg 64 MHz)
FIRC_clk
FXOSC_clk
CLKOUT
Selector
Peripheral
/1 to /32
/1 to /32
FIRC_clk_divided
FXOSC_clk_divided
eMIOS_1
(8ch)
eMIOS_0
(16ch)
/1 to /16
/1 to /16
Note : no clock monitor
associated with FMPLL1
FMPLL1
PLL1_Clk
(e.g. 64 MHz)
/1 to /32
Optional Clock to LCD
in Standby modes
SXOSC_clk_divided
SIRC_clk_divided
FIRC_clk_divided
FXOSC_clk_divided
Clock
Selector
Clock
Selector
FXOSC_clk
PLL0_Clk
Clock Monitor
Unit
FIRC_clk
FXOSC_clk
Clock
Selector
SXOSC_clk
SIRC_clk
PLL1_Clk
PLL0_Clk
Display
Controller
Unit
DCU
Clock
Selector
FIRC_clk
PLL0_Clk
ip_sync
Reset / INT
(128 kHz)
(4
– 16 MHz)
(4
– 16 MHz)
for emios
Set 3
/1 to /16
/1 to /16
/1 to /16
Peripheral
Set 1
Peripheral
Set 2
Auxiliary Clk0
Auxiliary Clk1
Auxiliary Clk2
Optional Clock to LCD
in standby modes
Selector
Clock
sys_clk/2
sys_clk
PLL1_clk
PLL1_clk/2
QuadSPI Serial Interface clk
Auxiliary Clk 3
Optional Clock to LCD
in Stop and Normal modes
Optional Clock to LCD
in Stop and Normal modes
FXOSC_clk_divided
FIRC_clk_divided
PLL0_Clk