NXP Semiconductors MPC5606S - Emios200 UC a Register (Emiosa[N])

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
246 Freescale Semiconductor
9.4.2.5 eMIOS200 UC A Register (EMIOSA[n])
Depending on the mode of operation, internal registers A1 or A2, used for matches and captures, can be
assigned to address EMIOSA[n]. Both A1 and A2 are cleared by reset. Table 9-14 summarizes the
EMIOSA[n] read and write accesses for all operation modes. For more information, see section
Section 9.5.1.1, UC modes of operation.
Address: eMIOS1 base address +0x0C Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0
CHDI
S23
CHDI
S22
CHDI
S21
CHDI
S20
CHDI
S19
CHDI
S18
CHDI
S17
CHDI
S16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-11. eMIOS200 Enable Channel Register (EMIOSUCDIS) for EMIOS200_1
Table 9-13. EMIOSUCDIS field descriptions
Field Description
CHDIS[n] Enable Channel [n] bit
The CHDIS[n] bit is used to disable each of the channels by stopping its respective clock.
0 Channel [n] enabled
1 Channel [n] disabled
Note: Channels that occupy a pair of slots are referred to by their lower slot number (LSB = 0
standard), therefore the bits corresponding to their higher slot number are reserved and read 0.
Address: UC[n] base address + 0x00 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
A
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-12. eMIOS200 UC A Register (EMIOSA[n])