NXP Semiconductors MPC5606S - Transmit FIFO Registers 0 - 14 (QSPI_TXFR0 - QSPI_TXFR14)

Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1017
30.4.3.9 Transmit FIFO Registers 0 – 14 (QSPI_TXFR0 – QSPI_TXFR14)
The QSPI_TXFR0–QSPI_TXFR14 registers provide visibility into the TX FIFO for debugging purposes.
Each register is an entry in the TX FIFO. The registers are read-only and cannot be modified.
Address: QSPI_BASE + 0x038
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R RXDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 30-8. POP RX FIFO Register (QSPI_POPR)
Table 30-21. QSPI_POPR field descriptions
Field Description
RXDATA RX Data. The RXDATA field contains the SPI data from the RX FIFO entry pointed to by the Pop Next
Data Pointer.
Address
:
QSPI_BASE+0x03C (QSPI_TXFR0)
...
QSPI_BASE+0x074 (QSPI_TXFR14)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R TXCMD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R TXDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 30-9. Transmit FIFO Registers 0 – 14 (QSPI_TXFR0 – QSPI_TXFR14)