IEEE 1149.1 Test Access Port Controller (JTAGC)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 721
19.8.3 TAP Controller state machine
The TAP controller is a synchronous state machine that interprets the sequence of logical values on the
TMS pin. Figure 19-5 shows the machine’s states. The value shown next to each state is the value of the
TMS signal sampled on the rising edge of the TCK signal.
As Figure 19-5 shows, holding TMS at logic 1 while clocking TCK through a sufficient number of rising
edges also causes the state machine to enter the Test-Logic-Reset state.
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