NXP Semiconductors MPC5606S - C.4 Changes between Revisions 3 and 4

Revision History
MPC5606S Microcontroller Reference Manual, Rev. 7
1330 Freescale Semiconductor
C.4 Changes between revisions 3 and 4
Flash Memory In the “Flash memory setting recommendations” section, changed “Master 3: DCU” to
“Master 4: DCU”.
Revised the LML[LLK] field description.
Revised the SLL[SLK] field description.
Revised the LMS[LSL] field description.
Changed the reset value of the following registers:
• NVPWD0 (was 0xFFFFFFFF, is 0xFEEDFACE)
• NVPWD1 (was 0xFFFFFFFF, is 0xCAFEBEEF)
IEEE 1149.1 Test
Access Port Controller
Added content to the “External signal description” section.
Internal Static RAM Changed the chapter title (was “Internal static RAM”, is “Static RAM”).
LIN Controller Replaced all RAM occurrences with “SRAM”.
In the “LIN mode features” section, added the “Peripheral DMA request sources“ item.
Mode Entry Module In the “Peripheral clock gating” section, changed “each peripheral” to “certain peripherals”.
Quad Serial Peripheral
Interface
Revised the “QuadSPI modes of operation” section.
Revised the “SCK — Serial Clock” section.
Real-Time Clock Revised the RTCC[APIVAL] field description.
In the RTCC[CLKSEL] field description, changed “32 kHz” to “32 KHz”.
In the “API functional description” section, changed “When the counter reaches the offset
count” to “When the counter reaches (offset count + 1)”.
In the “RTC functional description” section, added the text “RTCC[RTCVAL]=0x000 is
invalid.” to the third paragraph.
System Integration Unit
Lite
Revised the “SIUL block diagram” figure.
Revised the Features section.
Revised the “SIUL signal properties” table.
Revised the “External interrupt request input pins” section.
Revised the ISR, IRER, IREER, IFEER, IFER and PCRx figures.
Revised the “External interrupts” section.
Voltage Regulators and
Power Supplies
In the “Power domain organization” figure, moved the wakeup pads from PD1 to PD0.
Wakeup Unit In the IRER figure, revised the presentation of the EIRE field (was read-only, is read/write).
Appendix B Revised the MC_RGM entries.
Table C-4. Changes between revisions 3 and 4
Chapter Description
Throughout Editorial changes and improvements.
Rearranged the chapter order (alphabetical by module name).
Overview In the “System clocks and clock generation modules” section, changed “divider ratio (1 to
15)” to “divider ratio (1 to 16)”.
Table C-3. Changes between revisions 4 and 5 (continued)
Chapter Description