NXP Semiconductors MPC5606S - Development Control Register 1, 2 (DC1, DC2)

Nexus Development Interface (NDI)
MPC5606S Microcontroller Reference Manual, Rev. 7
962 Freescale Semiconductor
26.6.2.3 Development Control Register 1, 2 (DC1, DC2)
The development control registers are used to control the basic development features of the Nexus module.
Figure 26-5 shows development control register 1 and Table 26-5 describes the register’s fields.
MCKO_DIV MCKO Division Factor. The value of this signal determines the frequency of MCKO relative to the
system clock frequency when MCKO_EN is asserted. In this table, SYS_CLK represents the
system clock frequency.
Note: If the Nexus clock divider (NPC_PCR[MCKO_DIV]) is set to 8 and the Nexus clock gating
control (NPC_PCR[MCKO_GT]) is enabled, the Nexus clock (MCKO) will be disabled prior
to the completion of transmission of the Nexus message data. Do not enable the automatic
clock gating mode when the Nexus clock divider is set to 8.
EVT_EN EVTO/EVTI Enable. This bit enables the EVTO/EVTI port functions.
0 EVTO/EVTI port disabled.
1 EVTO/EVTI port enabled.
LP_DBG_EN Low-Power Debug Enable. The LP_DBG_EN bit enables debug functionality to support entry and
exit from low-power sleep and Stop modes.
0 Low-power debug disabled.
1 Low-power debug enabled.
SLEEP_SYNC Sleep Mode Synchronization. The SLEEP_SYNC bit is used to synchronize the entry into sleep
mode between the device and the debug tool. The device sets this bit before a pending entry into
sleep mode. After reading SLEEP_SYNC as set, the debug tool then clears SLEEP_SYNC to
acknowledge to the device that it may enter sleep mode.
0 Sleep mode entry acknowledge.
1 Sleep mode entry pending.
STOP_SYNC Stop Mode Synchronization. The STOP_SYNC bit is used to synchronize the entry into Stop
mode between the device and the debug tool. The device sets this bit before a pending entry into
Stop mode. After reading STOP_SYNC as set, the debug tool then clears STOP_SYNC to
acknowledge to the device that it may enter Stop mode.
0 Stop mode entry acknowledge.
1 Stop mode entry pending
PSTAT_EN Processor Status Mode Enable.
Table 26-4. PCR field descriptions (continued)
Field Description
MCKO_DIV[2:0] MCKO Frequency
0b000 SYSCLK1
0b001 SYSCLK2
0b010 Reserved
0b011 SYS_CLK4
0b100 Reserved
0b101 Reserved
0b110 Reserved
0b111 SYS_CLK8