NXP Semiconductors MPC5606S - Page 965

Nexus Development Interface (NDI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 963
Nexus
Reg:
0x0002 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R OPC MCK_DIV
EOC
0
PTM WEN
0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
OVC EIC TM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 26-5. Development Control Register 1 (DC1)
Table 26-5. DC1 field descriptions
Field Description
0
OPC
1
Output Port Mode Control.
0 Reduced-Port mode configuration (2 MDO pins).
1 Full-Port mode configuration (4 MDO pins).
1–2
MCK_DIV[1:0]
1
MCKO Clock Divide Ratio (see note 1).
00 MCKO is 1× processor clock frequency.
01 MCKO is 1/2× processor clock frequency.
10 MCKO is 1/4× processor clock frequency.
11 MCKO is 1/8× processor clock frequency.
3–4
EOC[1:0]
EVTO Control.
00 EVTO upon occurrence of watchpoints (configured in DC2).
01 EVTO upon entry into debug mode.
10 EVTO upon timestamping event.
11 Reserved.
5 Reserved
6
PTM
Program Trace Method.
0 Program trace uses traditional branch messages.
1 Program trace uses branch history messages.
7
WEN
Watchpoint Trace Enable.
0 Watchpoint messaging disabled.
1 Watchpoint messaging enabled.
8–23 Reserved.
24–26
OVC[2:0]
Overrun Control.
000 Generate overrun messages.
001–010 Reserved.
011 Delay processor for BTM / DTM / OTM overruns.
1XX Reserved.