NXP Semiconductors MPC5606S - Page 966

Nexus Development Interface (NDI)
MPC5606S Microcontroller Reference Manual, Rev. 7
964 Freescale Semiconductor
Development control register 2 is shown in Figure 26-6 and its fields are described in Table 26-6.
27–28
EIC[1:0]
EVTI Control.
00 EVTI is used for synchronization (program trace/data trace).
01 EVTI is used for debug request.
1X Reserved.
29–31
TM[2:0]
Trace Mode. Any or all of the TM bits may set, enabling one or more traces.
000 No trace.
1XX Program trace enabled.
X1X Data trace enabled (not supported mode)
XX1 Ownership trace enabled.
1
The output port mode control bit (OPC) and MCKO divide bits (MCK_DIV) are shown for clarity. These functions
are controlled globally by the NPC port control register (PCR). These bits are writable in the PCR but have no effect.
Nexus
Reg:
0x0003 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
EWC
0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 26-6. Development Control Register 2 (DC2)
Table 26-6. DC2 field descriptions
Field Description
0–7
EWC[7:0]
EVTO Watchpoint Configuration. Any or all of the bits in EWC may be set to configure the EVTO
watchpoint.
00000000 No Watchpoints trigger EVTO
1XXXXXXX Watchpoint #0 (IAC1 from Nexus1) triggers EVTO.
X1XXXXXX Watchpoint #1 (IAC2 from Nexus1) triggers EVTO.
XX1XXXXX Watchpoint #2 (IAC3 from Nexus1) triggers EVTO.
XXX1XXXX Watchpoint #3 (IAC4 from Nexus1) triggers EVTO.
XXXX1XXX Watchpoint #4 (DAC1 from Nexus1) triggers EVTO.
XXXXX1XX Watchpoint #5 (DAC2 from Nexus1) triggers EVTO.
XXXXXX1X Watchpoint #6 (DCNT1 from Nexus1) triggers EVTO.
XXXXXXX1 Watchpoint #7 (DCNT2 from Nexus1) triggers EVTO.
8–31 Reserved.
Table 26-5. DC1 field descriptions (continued)
Field Description