NXP Semiconductors MPC5606S - Reset Mode Configuration Register (ME_RESET_MC)

Mode Entry Module (MC_ME)
MPC5606S Microcontroller Reference Manual, Rev. 7
922 Freescale Semiconductor
25.3.2.8 Reset Mode Configuration Register (ME_RESET_MC)
This register configures system behavior during Reset mode. Please refer to Table 25-11 for details.
CDP_PRPH
_64_95
Clock Disable Process Pending status for Peripherals 64…95 — This bit is set when any peripheral appearing
in ME_PS2 has been requested to have its clock disabled. It is cleared when all these peripherals which have
been requested to have their clocks disabled have entered the state in which their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
CDP_PRPH
_32_63
Clock Disable Process Pending status for Peripherals 32…63 — This bit is set when any peripheral appearing
in ME_PS1 has been requested to have its clock disabled. It is cleared when all these peripherals which have
been requested to have their clocks disabled have entered the state in which their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
CDP_PRPH
_0_31
Clock Disable Process Pending status for Peripherals 0…31 — This bit is set when any peripheral appearing in
ME_PS0 has been requested to have its clock disabled. It is cleared when all these peripherals which have been
requested to have their clocks disabled have entered the state in which their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
Address 0xC3FD_C020 Access: Supervisor read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 0 0 0 0 0 PDO 0 0
MVRON
DFLAON CFLAON
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0 0 0 0 0 0 0
FMPLL1ON FMPLL0ON
FXOSCON
FIRCON
SYSCLK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Figure 25-9. Invalid Mode Transition Status Register (ME_IMTS)
Table 25-10. Debug Mode Transition Status Register (ME_DMTS) field descriptions (continued)
Field Description