NXP Semiconductors MPC5606S - Overview

Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
334 Freescale Semiconductor
12.1.1 Overview
Figure 12-1. DCU block diagram
Figure 12-1 shows the DCU architecture. This comprises two distinct sections. The lower section shows
the functional blocks of the DCU that fetch the graphic and video content and drive the TFT LCD panel.
The upper section describes the user interface through which the user configures the graphical content of
the TFT LCD panel.
Registers
Interface
(control
Layer0
Layer1
Layer2
Pixel
Format
Converter
Blending
Gamma
Correction
out
FIFO
Display
Driver
Parallel
data
Interface
Gamma
dcu_clk
pdi_clk
pdi_datain[17:0]
AHB
Master
I/F
External
Video
TFT
display
pdi_hsync
pdi_vsync
Timing and
Control
Unit
pix_clk_in
pdi_clk
MUX
clk,hsync,vsync
Timing signals to other modules
Mode
RAM
Cursor
. . .
Layer14
Layer15
BGCOLOR
(1 KB)
(256 x 8 x3)
Signature
Calculator
CRC_ready interrupt
CRC value
CH1
CH2
CH3
CH4
CLUT/
Tile
RAM
In FIFO
(6KB)
CRC pos
descriptors
for each
layer)
Slave bus I/F
In FIFO
In FIFO
In FIFO
RAM
Source