NXP Semiconductors MPC5606S - Flash ECC Address Register (FEAR)

Error Correction Status Module (ECSM)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 535
If an attempt to force a non-correctable inversion (by asserting EEGR[FRCNCI] or EEGR[FRC1NCI])
and EEGR[ERRBIT] equals 64, then no data inversion will be generated.
16.4.2.11 Flash ECC Address Register (FEAR)
The FEAR is a 32-bit register for capturing the address of the last properly enabled ECC event in the flash
memory. Depending on the state of the ECC Configuration Register, an ECC event in the flash memory
causes the address, attributes, and data associated with the access to be loaded into the FEAR, FEMR,
FEAT, and FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register to be
asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 16-10 and Table 16-11 for the Flash ECC Address Register definition.
9-15
ERRBIT
[0:6]
Error Bit Position
The vector defines the bit position which is complemented to create the data inversion on the write
operation. For the creation of 2-bit data inversions, the bit specified by this field plus the odd parity bit of
the ECC code are inverted.
The RAM controller follows a vector bit ordering scheme where LSB=0. Errors in the ECC syndrome bits
can be generated by setting this field to a value greater than the RAM width. For example, consider a
32-bit RAM implementation.
The 32-bit ECC approach requires 7 code bits for a 32-bit word. For PRAM data width of 32 bits, the
actual SRAM (32b data + 7b for ECC) = 39 bits. The following association between the ERRBIT field and
the corrupted memory bit is defined:
if ERRBIT = 0, then RAM[0] of the odd bank is inverted
if ERRBIT = 1, then RAM[1] of the odd bank is inverted
...
if ERRBIT = 31, then RAM[31] of the odd bank is inverted
if ERRBIT = 64, then ECC Parity[0] of the odd bank is inverted
if ERRBIT = 65, then ECC Parity[1] of the odd bank is inverted
...
if ERRBIT = 70, then ECC Parity[6] of the odd bank is inverted
For ERRBIT values of 32 to 63 and greater than 70, no bit position is inverted.
Address: Base + 0x0050 Access: User read-only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R FEAR[0:15]
W
Reset —
1
1
Value is undefined at reset.
— — — — — — — — — — — — — — —
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R FEAR[16:31]
W
Reset — — — — — — — — — — — — — — — —
Figure 16-10. Flash ECC Address Register (FEAR)
Table 16-10. ECC Error Generation (EEGR) field descriptions (continued)
Name Description