NXP Semiconductors MPC5606S - Control Register (CTRL)

FlexCAN
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 683
18.3.4.2 Control Register (CTRL)
This register is defined for specific FlexCAN control features related to the CAN bus, such as bit-rate,
programmable sampling point within an Rx bit, Loopback mode, Listen-Only mode, Bus Off recovery
behavior, and interrupt enabling (Bus-Off, Error, Warning). It also determines the division factor for the
clock prescaler. Most of the fields in this register should only be changed while the module is in Disable
mode or in Freeze mode. Exceptions are the BOFF_MSK, ERR_MSK, TWRN_MSK, RWRN_MSK, and
BOFF_REC bits, which can be accessed at any time.
IDAM ID Acceptance Mode
This 2-bit field identifies the format of the elements of the Rx FIFO filter table, as shown in
Tabl e 18-9. Note that all elements of the table are configured at the same time by this field (they are
all the same format). See Section 18.3.3, Rx FIFO Structure.
MAXMB Maximum Number of Message Buffers
This 6-bit field defines the maximum number of message buffers that will take part in the matching
and arbitration processes. The reset value (0x0F) is equivalent to 16 MB configuration. This field
should be changed only while the module is in Freeze mode.
Maximum MBs in use = MAXMB + 1
Note: MAXMB has to be programmed with a value smaller than or equal to the number of available
Message Buffers; otherwise FlexCAN will not transmit or receive frames.
Note: When the Rx FIFO is enabled, it uses 8 MBs. These should be included in the MAXMB total.
Thus, for example, if the Rx FIFO and 4 other MBs are enabled, MAXMB = 11.
Table 18-9. IDAM coding
IDAM Format Explanation
00 A One full ID (standard or extended) per filter element.
01 B Two full standard IDs or two partial 14-bit extended IDs per filter element.
10 C Four partial 8-bit IDs (standard or extended) per filter element.
11 D All frames rejected.
Address: Base + 0x0004 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
PRESDIV RJW PSEG1 PSEG2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BOFF
_MSK
ERR
_ MSK
CLK
_SRC
LPB
TWRN
_MSK
RWRN
_MSK
0 0
SMP
BOFF _REC TSYN
LBUF
LOM PROPSEG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Figure 18-6. Control Register (CTRL)
Table 18-8. MCR field descriptions (continued)
Field Description