Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
1056 Freescale Semiconductor
4. The DMA will continue to fill TX FIFO until it is full or step 5 occurs.
5. Disable QuadSPI DMA transfers by disabling the DMA enable request for the DMA channel
assigned to TX FIFO and RX FIFO. This is done by clearing the corresponding DMA enable
request bits in the DMA Controller.
6. Ensure all received data in RX FIFO has been transferred to memory receive queue by reading the
RXCNT in QSPI_SPISR or by checking RFDF in the QSPI_SPISR after each read operation of the
QSPI_POPR.
7. Modify DMA descriptor of TX and RX channels for “new” queues
8. Flush TX FIFO by writing a 1 to the CLR_TXF bit in the QSPI_MCR, Flush RX FIFO by writing
a 1 to the CLR_RXF bit in the QSPI_MCR.
9. Clear transfer count either by setting CTCNT bit in the command word of the first entry in the new
queue or via CPU writing directly to SPI_TCNT field in the QSPI_TCR.
10. Enable DMA channel by enabling the DMA enable request for the DMA channel assigned to the
QuadSPI TX FIFO, and RX FIFO by setting the corresponding DMA set enable request bit.
11. Enable serial transmission and serial reception of data by clearing the EOQF bit.
30.6.2 Baud rate settings—SPI modes only
Table 30-47 shows the baud rate that is generated based on the combination of the baud rate prescaler PBR
and the baud rate scaler BR in the QSPI_CTAR registers. The values calculated cover the most usual bus
frequencies. They assume that the double baud rate DBR bit is clear. Note that they are rounded
appropriately.
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