NXP Semiconductors MPC5606S - DSPI Transfer Count Register (Dspix_Tcr)

Deserial Serial Peripheral Interface (DSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 293
11.7.2.2 DSPI Transfer Count Register (DSPIx_TCR)
The DSPIx_TCR contains a counter that indicates the number of SPI transfers made. The transfer counter
is intended to assist in queue management. The user must not write to the DSPIx_TCR while the DSPI is
running.
Table 11-4 describes the field in the DSPI transfer count register.
11.7.2.3 DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn)
The DSPI modules each contain eight clock and transfer attribute registers (DSPIx_CTARn) which are
used to define different transfer attribute configurations. Each DSPIx_CTAR controls:
•Frame size
• Baud rate and transfer delay values
24–30 Reserved.
31
HALT
Halt. Provides a mechanism for software to start and stop DSPI transfers. Refer to Section 11.8.2,
Start and stop of DSPI transfers, for details on the operation of this bit.
0 Start transfers
1 Stop transfers
Address: Base + 0x0008 Access:User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
SPI_TCNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 11-4. DSPI Transfer Count Register (DSPIx_TCR)
Table 11-4. DSPIx_TCR field descriptions
Field Description
0–15
SPI_TCNT
[0:15]
SPI transfer counter. Counts the number of SPI transfers the DSPI makes. The SPI_TCNT field is incremented
every time the last bit of an SPI frame is transmitted. A value written to SPI_TCNT presets the counter to that value.
SPI_TCNT is reset to zero at the beginning of the frame when the CTCNT field is set in the executing SPI
command. The transfer counter wraps around—in other words, incrementing the counter past 65535 resets the
counter to zero.
16–31 Reserved.
Table 11-3. DSPIx_MCR field descriptions (continued)
Field Description