Deserial Serial Peripheral Interface (DSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
294 Freescale Semiconductor
• Clock phase
• Clock polarity
• MSB or LSB first
At the initiation of an SPI transfer, control logic selects the DSPIx_CTAR that contains the transfer’s
attributes.Do not write to the DSPIx_CTARs while the DSPI is running.
In Master mode, the DSPIx_CTARn registers define combinations of transfer attributes such as frame size,
clock phase and polarity, data bit ordering, baud rate, and various delays. In Slave mode, a subset of the
bit fields in the DSPIx_CTAR0 and DSPIx_CTAR1 registers are used to set the slave transfer attributes.
Refer to the individual bit descriptions for details on which bits are used in Slave modes.
When the DSPI is configured as an SPI master, the CTAS field in the command portion of the TX FIFO
entry selects which of the DSPIx_CTAR registers is used on a per-frame basis. When the DSPI is
configured as an SPI bus slave, the DSPIx_CTAR0 register is used.
.
Address:
Base + 0x000C (DSPIx_CTAR0)
Base + 0x0010 (DSPIx_CTAR1)
Base + 0x0014 (DSPIx_CTAR2)
Base + 0x0018 (DSPIx_CTAR3)
Base + 0x001C (DSPIx_CTAR4)
Base + 0x0020 (DSPIx_CTAR5)
Base + 0x0024 (DSPIx_CTAR6)
Base + 0x0028 (DSPIx_CTAR7) Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
DBR FMSZ
CPO
L
CPH
A
LSB
FE
PCSSCK PAS C PDT PBR
W
Reset 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CSSCK ASC DT BR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 11-5. DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn)
Table 11-5. DSPIx_CTARn field descriptions
Field Descriptions
0
DBR
Double Baud Rate. The DBR bit doubles the effective baud rate of the Serial Communications Clock
(SCK). This field is used only in Master mode. It effectively halves the baud rate division ratio
supporting faster frequencies and odd division ratios for the SCK. When the DBR bit is set, the duty
cycle of the SCK depends on the value in the Baud Rate Prescaler and the Clock Phase bit as listed
in
Tabl e 11-6. See the BR field description for details on how to compute the baud rate. If the overall
baud rate is the system clock divided by two or divided by three, then neither the Continuous SCK
Enable nor the Modified Timing Format Enable bits should be set.
0 The baud rate is computed normally with a 50/50 duty cycle
1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler
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