Deserial Serial Peripheral Interface (DSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 295
1–4
FMSZ[0:3]
Frame Size. The FMSZ field selects the number of bits transferred per frame. The FMSZ field is used
in Master mode and Slave mode.
Ta ble 11-7 lists the frame size encodings.
When operating in TSB confirmation, the FMSZ defines the point within the 32-bit (maximum length)
frame where control of the CS switches from the DSPI_DSICR to the DSPI_DSICR1 register. The
crossover point must range between 4 bits and 16 bits and is encoded as indicated in
Tabl e 11-7. The
remaining frame after the crossover point, regardless of how many bits are remaining, will be
controlled by the DSPI_DSICR1 register.
5
CPOL
Clock Polarity. The CPOL bit selects the inactive state of the Serial Communications Clock (SCK).
This bit is used in both Master and Slave mode. For successful communication between serial
devices, the devices must have identical clock polarities. When the continuous selection format (see
Section 11.8.5.5, Continuous selection format) is selected, switching between clock polarities without
stopping the DSPI can cause errors in the transfer due to the peripheral device interpreting the switch
of clock polarity as a valid clock edge.
0 The inactive state value of SCK is low
1 The inactive state value of SCK is high
6
CPHA
Clock Phase. The CPHA bit selects which edge of SCK causes data to change and which edge
causes data to be captured. This bit is used in both Master and Slave mode. For successful
communication between serial devices, the devices must have identical clock phase settings.
Continuous SCK is only supported for CPHA=1.
0 Data is captured on the leading edge of SCK and changed on the following edge
1 Data is changed on the leading edge of SCK and captured on the following edge
7
LSBFE
LSB First. The LSBFE bit selects if the LSB or MSB of the frame is transferred first. This bit is used
only in Master mode. When operating in TSB configuration, this bit should always be 1.
0 Data is transferred MSB first
1 Data is transferred LSB first
8–9
PCSSCK[0:1
]
PCS to SCK Delay Prescaler. The PCSSCK field selects the prescaler value for the delay between
assertion of PCS and the first edge of the SCK. This field is used only in Master mode. The table
below lists the prescaler values. See the CSSCK[0:3] field description for details on how to compute
the PCS to SCK Delay.
Table 11-5. DSPIx_CTARn field descriptions (continued)
Field Descriptions
PCSSCK PCS to SCK delay prescaler value
00 1
01 3
10 5
11 7
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